Analytic Performance Modeling for a Spectrum of Multithreaded Processor Architectures

The throughput of pipelined processors suflers from delays associated with instruction dependencies and memory latencies. Multithreaded architectures attempt t o hide such delays b y sharing the processor with multiple instruction streams. In this paper we develop a comprehensive analytic framework to quantitatively evaluate the performance of a wide spectrum of multithreaded machines, ranging f r o m those that are capable of switching threads every cycle to those that switch threads only on long delays. The models are validated against previously published simulation and modeling results, and then used to assess the performance potential of multithreading given current processor techno logy .